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74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
March 1994 Revised November 1999
74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation.
Features
s Separate control logic for each byte s 16-bit version of the ABT374 s Edge-triggered D-type inputs s Buffered Positive edge-triggered clock s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Guaranteed latch-up protection
Ordering Code:
Order Number 74ABT16374CSSC 74ABT16374CMTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Name OEn CPn D0-D15 O0-O15 Description 3-STATE Output Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Data Inputs 3-STATE Outputs
(c) 1999 Fairchild Semiconductor Corporation
DS011668
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74ABT16374
Functional Description
The ABT16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
Truth Tables
Inputs CP1 Outputs D0-D7 H L X X O0-O7 H L (Previous) Z Outputs D8-D15 H L X X O8-O15 H L (Previous) Z

L X
OE1 L L L H Inputs
CP2

L X
OE2 L L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
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74ABT16374
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current: OE Pin (Across Comm Operating Range) Other Pins Over Voltage Latchup (I/O) -500 mA 10V -350 mA twice the rated IOL (mA) -0.5V to 5.5V -0.5V to VCC -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100mV/ns -40C to +85C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ I CCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test 4.75 2.5 2.0 0.55 1 1 7 -1 -1 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A V A A mA A A mA mA mA mA mA mA mA/ 0.30 MHz Max Min Min Min Min Max Max Max 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -32 mA IOL = 64 mA VIN = 2.7V (Note 3) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 A All Other Pins Grounded Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE ICCD Dynamic ICC (Note 3) No Load -100 10 -10 -275 50 100 2.0 62 2.0 2.5 2.5 2.5 0-5.5V 0-5.5V Max Max 0.0 Max Max Max VOUT = 2.7V; OE = 2.0V VOUT = 0.5V; OE = 2.0V VOUT = 0.0V VOUT = V CC VOUT = 5.5V; All Others VCC or GND All Outputs HIGH All Outputs LOW OE = VCC; All Others at VCC or GND VI = VCC - 2.1V Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCCor GND Max Outputs Open OE = GND, (Note 4) One Bit Toggling, 50% Duty Cycle
Note 3: Guaranteed, but not tested. Note 4: For 8-bit toggling, ICCD < 0.8 mA/MHz.
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74ABT16374
AC Electrical Characteristics
(SSOP Package) TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable Time 150 1.8 1.8 1.2 1.6 2.2 2.2 6.2 5.9 5.6 5.3 7.1 6.6 VCC = +5.0V CL = 50 pF Typ Max Min 150 1.8 1.8 1.2 1.6 2.2 2.2 6.2 5.9 5.6 5.3 7.1 6.6 TA = -40C to +85C V CC = 4.5V to 5.5V CL = 50 pF Max MHz ns ns ns Units
AC Operating Requirements
TA = +25C Symbol Parameter V CC = +5.0V CL = 50 pF Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Pulse Width, CP HIGH or LOW 1.1 1.1 1.3 1.3 3.0 3.0 Max Min 1.1 1.1 1.3 1.3 3.0 3.0 TA = -40C to +85C VCC = 4.5V to 5.5V CL = 50 pF Max ns ns ns Units
Capacitance
Symbol CIN COUT (Note 5) Parameter Input Capacitance Output Capacitance Typ 5.0 11.0 Units pF pF VCC = 0V VCC = 5.0V Conditions (TA = 25C)
Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74ABT16374
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74ABT16374 16-Bit D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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